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16M x 4-Bit Dynamic RAM (4k & 8k Refresh, EDO-version) HYB 3164405J/T(L) -50/-60 HYB 3165405J/T(L) -50/-60 Preliminary Information * * * * * * * * * * * 16 777 216 words by 4-bit organization 0 to 70 C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 60 ns (-60 version) Cycle time: 84 ns (-50 version) 104 ns (-60 version) CAS access time: 13 ns ( -50 version) 15 ns ( -60 version) Hyper page mode (EDO) cycle time 20 ns (-50 version) 25 ns (-60 version) Single + 3.3 V ( 0.3V) power supply Low power dissipation max. 396 active mW ( HYB 3164405J/T(L)-50) max. 360 active mW ( HYB 3164405J/T(L)-60) max. 504 active mW ( HYB 3165405J/T(L)-50) max. 432 active mW ( HYB 3165405J/T(L)-60) 7.2 mW standby (TTL) 720 W standby (MOS) 14.4 mW Self Refresh (L-version only) Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh modes Hyper page mode (EDO) capability 8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164405J/T(L)) 4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165405J/T(L)) Plastic Package: P-SOJ-34-1 500 mil HYB 3164(5)400J P-TSOPII-34-1 500 mil HYB 3164(5)400T Semiconductor Group 89 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM This HYB3164(5)405 is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)405 operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)400J/T to be packaged in a 500mil wide SOJ-34 or TSOP-34 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)405TL parts have a very low power sleep mode" supported by Self Refresh. Ordering Information Type HYB 3164405J-50 HYB 3164405J-60 HYB 3164405T-50 HYB 3164405T-60 Ordering Code on request on request on request on request Package P-SOJ-34-1 P-SOJ-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-SOJ-34-1 P-SOJ-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-TSOPII-34-1 Descriptions 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) HYB 3164405TL-50 on request HYB 3164405TL-60 on request HYB 3165405J-50 HYB 3165405J-60 HYB 3165405T-50 HYB 3165405T-60 on request on request on request on request HYB 3165405TL-50 on request HYB 3165405TL-60 on request Pin Names A0-A12 A0-A11 RAS OE I/O1-I/O4 CAS WRITE Vcc Vss Address Inputs for HYB 3164405J/T(L) Address Inputs for HYB 3165405J/T(L) Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground Semiconductor Group 90 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM P-SOJ-34-1 (500 mil) P-TSOPII-34-1 (500 mil) Pin Configuration Semiconductor Group 91 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM TRUTH TABLE FUNCTION Standby Read Early-Write Delayed-Write Read-Modify-Write Hyper Page Mode Read 1st Cycle 2nd Cycle Hyper Page Mode Write 1st Cycle 2nd Cycle Hyper Page Mode RMW 1st Cycle 2st Cycle RAS only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh READ WRITE Self Refresh (L-version only) RAS H L L L L L L L L L L L H-L H-L L-H-L L-H-L H-L CAS H-X L L L L H-L H-L H-L H-L H-L H-L H L L L L L WRITE X H L H-L H-L H H L L H-L H-L X H L H L H OE X L X H L-H L L X X L-H L-H X X X L X X ROW ADDR X ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW X X ROW ROW X COL ADDR X COL COL COL COL COL COL COL COL COL COL n/a n/a n/a COL COL X I/O1I/O4 High Impedance Data Out Data In Data In Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance High Impedance Data Out Data In High Impedance Semiconductor Group 92 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM Block Diagram for HYB 3164405J/T(L) Semiconductor Group 93 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM Block Diagram for HYB 3165405J/T(L) Semiconductor Group 94 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.0 W Data out current (short circuit)..................................................................................................50 mA Note Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V, (values in brackets for HYB 3165405J/T) Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output H" level voltage (Iout = -2mA) Output low voltage (LVTTL) Output L"level voltage (Iout = +2mA) Output high voltage (LVCMOS) Output H" level voltage (Iout = -100uA) Ouput low voltage (LVCMOS) Output L" level voltage (Iout = +100uA) Input leakage current,any input (0 V < Vin < Vcc , all other pins = 0 V Symbol Limit Values min. max. Vcc+0.3 0.8 - 0.4 2.0 - 0.3 2.4 - Unit Note V V V V V V A A 1) 1) VIH VIL VOH VOL VOH VOL II(L) IO(L) ICC1 -50 ns version -60 ns version Vcc-0.2 -2 -2 0.2 2 2 Output leakage current (DO is disabled, 0 V < Vout < Vcc ) Average Vcc supply current: - - 110 (140) mA 100 (120) mA 2 mA 2) 3) 4) (RAS, CAS, address cycling: tRC = tRC min.) Standby Vcc supply current (RAS=CAS= Vih) ICC2 - - Semiconductor Group 95 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V, (values in brackets for HYB 3165405J/T) Parameter Symbol Limit Values min. Average Vcc supply current, during RAS-only ICC3 refresh cycles: -50 ns version -60 ns version (RAS cycling: CAS = VIH: tRC = tRC min.) Unit Note max. 110 (140) mA 100 (120) mA 2) 4) - - Average Vcc supply current, during hyperpage mode (EDO): -50 ns version -60 ns version ICC4 - - 115 (150) mA 100 (120) mA 200 A 2) 3) 4) (RAS = VIL, CAS, address cycling: tHPC=tHPC min.) Standby Vcc supply current (RAS=CAS= Vcc-0.2V) ICC5 - - Average Vcc supply current, during CAS-before- ICC6 RAS refresh mode: -50 ns version -60 ns version (RAS, CAS cycling: tRC = tRC min.) - - - 110 (140) mA 100 (120) mA 400 A 2) 4) Self Refresh Current (L-version only) Average Power Supply Current during Self Refresh. (CBR cycle with tRAS>TRASSmin, CAS held low, WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V) ICC7 Capacitance TA = 0 to 70 C,VCC = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (A0 to A11,A12) Input capacitance (RAS, CAS, WRITE, OE) I/O capacitance (I/O1-I/O4) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit CI1 CI2 CIO Semiconductor Group 96 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM AC Characteristics 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter Symbol Limit Values -50 min. max. min. -60 max. Unit Note common parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for HYB3164405 Refresh period for HYB3165405 tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF 84 30 50 8 0 8 0 8 12 10 8 45 5 1 - - - 50 128 64 - - 100k 10k - - - - 37 25 104 40 60 10 0 10 0 10 14 12 10 50 5 1 - - - - 100k 10k - - - - 45 30 - - - 50 128 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7 Read Cycle Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time tRAC tCAC tAA tOEA tRAL tRCS tRCH - - - - 25 0 0 0 50 13 25 13 - - - - - - - - 30 0 0 0 60 15 30 15 - - - - ns ns ns ns ns ns ns ns 11 11 8, 9 8, 9 8,10 Read command hold time referenced to tRRH RAS Semiconductor Group 97 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter Symbol Limit Values -50 min. max. - 13 13 - - - - min. 0 0 0 0 0 15 15 -60 max. - 15 15 - - - - Unit Note CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay tCLZ tOFF tOEZ tDZC tDZO tCDD tODD 0 0 0 0 0 13 13 ns ns ns ns ns ns ns 8 12 12 13 13 14 14 Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 8 7 0 8 8 0 7 - - - - - - - 10 10 0 10 10 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15 Read-modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 111 67 30 42 7 - - - - - 135 79 34 49 10 - - - - - ns ns ns ns ns 15 15 15 Hyper Page Mode (EDO) Cycle Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in hyper page mode tHPC tCP tCPA tCOH tRAS 20 8 - 5 50 - - 27 - 200k 25 10 - 5 60 - - 35 - 200k ns ns ns ns ns 7 Semiconductor Group 98 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter Symbol Limit Values -50 min. max. - - - - 10 min. 35 10 10 10 0 -60 max. - - - - 10 Unit Note CAS precharge to RAS Delay OE pulse width OE hold time from CAS high tRHCP tOEP tOEHC 27 7 7 7 0 ns ns ns ns ns WE pulse width to output disable at CAS tWPZ high Output buffer turn-off delay from WE tWPZ Hyper Page Mode (EDO) Readmodify-Write Cycle Hyper page mode (EDO) read-write cycle time CAS precharge to WE tPRWC tCPWD 51 41 - - 66 49 - - ns ns CAS before RAS refresh cycle CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 5 8 5 8 8 - - - - - 5 10 5 10 10 - - - - - ns ns ns ns ns CAS-before-RAS counter test cycle CAS precharge time (CAS-before-RAS counter test cycle) tCPT 35 - 40 - ns Self Refresh Cycle RAS pulse width during self refresh CAS hold time during self refresh tRASS tCHS 100k 84 -50 _ _ _ 100k 104 -50 _ _ _ ns ns ns 17 17 17 RAS precharge time during self refresh tRPS Semiconductor Group 99 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM AC Characteristics (cont'd) 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3V , tT = 2 ns Parameter Symbol Limit Values -50 min. max. - - min. 10 10 -60 max. - - Unit Note Test Mode Write command setup time Write command hold time tWTS tWTH 10 10 ns ns 18) 18) Semiconductor Group 100 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM Notes: 1) All voltages are referenced to VSS. Vih may overshoot to VV + 0.2V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. 2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a hyper page mode cycle ( thpc). 5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh. If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh 18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value. These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must be adjusted by 5 ns. Semiconductor Group 101 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRC tRAS RAS V IH VIL tRP tCSH tRCD tRSH tCAS tRAL tCRP V IH CAS VIL tRAD tASR tASC tCAH Column tASR Row Address V IH VIL Row tRCH tRAH tRCS tRRH tAA tOEA WE V IH VIL OE V IH VIL tDZC tDZO tCAC tCLZ Hi Z tCDD tODD I/O (Inputs) V IH VIL tOFF tOEZ Valid Data Out Hi Z I/O (Outputs) V V OH OL tRAC "H" or "L" WL1 Read Cycle Semiconductor Group 102 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRC tRAS RAS V IH VIL tRP tCSH tRCD tRSH tCAS tRAL tCAH Column tCRP V IH CAS VIL tRAD tASR tASC tASR Row Address V IH VIL . Row tRAH WE V IH VIL tWCS t WP tCWL tWCH tRWL OE V IH VIL tDS I/O (Inputs) V IH VIL tDH Valid Data In OH I/O (Outputs) V OL V Hi Z "H" or "L" WL2 Write Cycle (Early Write) Semiconductor Group 103 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRC tRAS RAS V IH VIL tRP tCSH tRCD tRSH tCAS tRAL tCRP V IH CAS VIL tRAD tASR tASC tCAH Column tASR Row V IH . Address V IL Row tRAH WE V IH VIL tCWL tRWL tWP tOEH OE V IH VIL tDZO tDZC I/O (Inputs) V IH VIL tODD tDS tOEZ tCLZ tOEA tDH Valid Data OH I/O (Outputs) V OL V Hi-Z Hi-Z "H" or "L" WL3 Write Cycle (OE Controlled Write) Semiconductor Group 104 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRWC tRAS V IH VIL V IH tRP RAS tCSH tRCD tRSH tCAS tCRP CAS VIL tRAH tASR Address V IH VIL Row tCAH tASC Column tASR Row tRAD V IH tAWD tCWD tRWD tCWL tRWL tWP WE VIL tAA tRCS V IH tOEA tOEH OE VIL tDZO tDZC I/O (Inputs) V IH VIL tDS tDH Valid Data in tCLZ tCAC tODD tOEZ Data Out I/O (Outputs) V OL V OH tRAC "H" or "L" WL4 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 105 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRAS RAS V IH VIL tRP tRHCP tRSH tCRP tRCD tHPC tCRP V IH tCAS tCP tCAS tCAS CAS VIL tCSH tASR tRAH tASC Row tRAL tCAH tASC tCAH Column 2 tASC tCAH Column N Address V IH VIL Column 1 tRAD tRRH tRCH tRCS WE VIH VIL tOES OE V OH V OL tCAC tAA tCPA tCAC tAA tCPA tOFF tOEA tRAC tAA tCAC tOEZ tCOH tCOH Data Out 2 Data Out N I/O IH (Output) V IL V tCLZ Data Out 1 "H" or "L" WL5 Hyper Page Mode (EDO) Read Cycle Semiconductor Group 106 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRAS V IH tRP tRHCP tRSH tCRP tRCD RAS VIL tHPC tCRP V IH tCAS tCP tCAS tCAS CAS VIL tCSH tASR tRAH tASC Row tRAL tCAH tASC tCAH Column 2 tASC tCAH Column N Address V IH VIL Column 1 tRAD tRRH tRCH tCAC tAA tCPA tOEHC tOEHC tCAC tAA tCPA tRCS WE VIH VIL tOES V OH V OL tOFF tOEA tRAC tAA tCAC OE tOEP tOEZ tOEA tOEP tOEA tOEZ tOEZ Data Out 2 Data Out N I/O IH (Output) V IL V tCLZ Data Out 1 WL6 "H" or "L" Hyper Page Mode (EDO) Read Cycle (OE Control) Semiconductor Group 107 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRAS V IH tRP tRHCP tRSH tCRP tRCD RAS VIL tHPC tCRP V IH tCAS tCP tCAS tCAS CAS VIL tCSH tASR tRAH tASC Row tRAL tCAH tASC tCAH Column 2 tASC tCAH Column N Address V IH VIL Column 1 tRAD tAA tAA tRCH tRRH tRCH tRCS tRCS WE VIH VIL tRCH tRCS tWPZ tOES OE V OH V OL tCAC tCPA tWPZ tCAC tCPA tOFF tOEA tRAC tAA tCAC tOEZ tWHZ tWHZ I/O IH (Output) V IL "H" or "L" V tCLZ Data Out 1 Data Out 2 Data Out N WL7 Hyper Page Mode (EDO) Read Cycle (WE Control) Semiconductor Group 108 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRAS V IH tRP tRHCP tRSH tCRP tRCD RAS VIL tHPC tCRP V IH tCAS tCP tCAS tCAS CAS VIL tCSH tASR tRAH tASC Row Addr tRAL tCAH tASC tCAH Column 2 tASC tCAH Column N Address V IH VIL Column 1 tRAD tCWL tWCS VIH VIL tCWL tWCH tWP tWCS tRWL tCWL tWCH tWP tWCH tWCS tWP WE OE V OH V OL tDS V IH tDH tDS tDH tDS tDH I/O (Input) V IL Data In 1 Data In 2 Data In N "H" or "L" WL8 Hyper Page Mode (EDO) Early Write Cycle Semiconductor Group 109 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRAS V IH tRP tRCD tRSH tCP tCAS tCP tCAS tCRP RAS VIL tHPC tCRP V IH tCAS CAS VIL tCSH tASR tRAH tASC Row tRAL tCAH tASC tCAH Column 2 tASC tCAH Column N Address V IH VIL Column 1 tRAD tCWL tRCS tCWL tRCS tCWL tRWL tRCS WE VIH VIL tWP tOEH OE V OH V OL tWP tOEH tWP tOEH tODD tDS tODD tDH tDS tDH tODD tDS tDH I/O (Input) V IH VIL Data In 1 Data In 2 Data In N WL16 "H" or "L" Hyper Page Mode (EDO) Late Write Cycle Semiconductor Group 110 tRASP tRP tPRWC tCP tCAS tCAS tCAH tASC tASC Column Row Column V RAS IH V IL tCSH tRSH tCAS tRAL tCRP tRCD Semiconductor Group V CAS IH V IL tRAD tCAH tASC Column tASR tRAH tCAH tASR V Address IH V IL Row V tRCS tAA tOEA tOEA tWP tWP tOEA tAWD tAWD tAWD tRWD tCWD tCWL tCWL tCPWD tCWD tCPWD tCWD tRWL tCWL WE IH Hyper Page Mode (EDO) Read-Modify-Write Cycle V IL 111 tWP V IH OE V IL tCPA tDZC Data In tCPA tODD Data In V IH tDZC tCLZ tDZO tCLZ tCAC tRAC tOEZ tDH tAA tDS Data Out Data Out tDZC tCLZ tOEH tODD Data In I/O (Inputs) V IL tODD tOEH tOEZ tDS tDH tOEH tCAC tAA tDS Data Out tDH OH I/O (Outputs) V V OL HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM WL17 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRC tRAS RAS V IH VIL tRP tCRP tRPC V IH CAS VIL tRAH tASR tASR Row Address V IH VIL Row OH I/O (Outputs) V OL V HI-Z "H" or "L" WL9 RAS Only Refresh Cycle Semiconductor Group 112 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRC tRP RAS V IH VIL tRAS tRP tRPC tCP tCSR tCHR tRPC tCRP CAS V IH VIL tWRP tWRH V IH VIL WE tOEZ OE V IH VIL tCDD I/O (Inputs) V IH VIL tODD OH I/O (Outputs)VOL V HI-Z tOFF "H" or "L" WL10 CAS-before-RAS Refresh Cycle Semiconductor Group 113 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRC V IH VIL tRC tRP tRAS tRP tRAS RAS tRCD V IH VIL tRSH tCHR tCRP CAS tRAD tASC tASR tRAH Row tWRP tCAH tWRH tASR Row Address V IH VIL Column tRCS WE V IH VIL tRRH tAA tOEA OE V IH VIL tDZC tDZO tCDD tODD tCAC tCLZ I/O (Inputs) V IH VIL tOFF tOEZ Valid Data Out HI-Z tRAC OH I/O (Outputs) V OL V "H" or "L" WL11 Hidden Refresh Read Cycle Semiconductor Group 114 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRC tRP RAS V IH VIL tRC tRAS tRP tRAS tRCD V IH VIL tRSH tCHR tCRP CAS tRAD tRAH tASR tASC tCAH Column tASR Row Address V IH VIL Row tWCS tWCH tWP tWRP tWRH WE V IH VIL tDS I/O (Input) V IH V IL tDH Valid Data OH I/O (Output) V OL V HI-Z "H" or "L" WL12 Hidden Refresh Early Write Cycle Semiconductor Group 115 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRP RAS V IH VIL tRASS tRPS tRPC tCSR CAS V IH VIL tCHS tCRP tCP tWRP tWRH WE V IH VIL OE V IH VIL tCDD I/O (Inputs) V IH VIL tODD tOEZ OH I/O (Outputs) V OL V HI-Z tOFF "H" or "L" WL13 Self Refresh (Sleep Mode) Semiconductor Group 116 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRP RAS V IH VIL tRC tRAS tRP tRPC tCP tCSR tCHR tRPC tCRP CAS V IH VIL tASR tRAH Address IH VIL V Row tWTS WE V IH VIL tWTH OE V IH VIL I/O (Inputs) V IL V IH tODD HI-Z tCDD tOEZ I/O (Outputs) V V OH OL HI-Z tOFF "H" or "L" WL15 Test Mode Entry Cycle Semiconductor Group 117 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM tRAS Read Cycle: RAS V IH V IL tRP tCSR CAS V IH V IL tCHR tCP tRSH tCAS tRAL tASC Address V IH V IL tCAH tAA tCAC tASR Row Column tWRP WE V IH V IL V IH V IL V IH V IL VOH VOL tRRH tOEA tCDD tOFF tRCH tWRH tRCS tDZC tDZO tCLZ OE I/O (Inputs) tODD tOEZ Data Out I/O (Outputs) tWRP Write Cycle: WE V IH V IL tWCS tRWL tCWL tWCH tWRH OE V IH V IL tDS I/O (Inputs) I/O (Outputs) V IH V IL V IH V IL tDH Data In HI-Z CAS-before-RAS Refresh Counter Test Cycle Semiconductor Group 118 HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM Package Outlines P-SOJ-34-1 (500 mil) (Plastic Small Outline J-leaded Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 119 Dimensions in mm HYB3164(5)405J/T(L)-50/-60 16M x 4-DRAM P-TSOPII-34-1 (500 mil) (Plastic Thin Small Outline Package Type II Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 120 Dimensions in mm |
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